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preliminary rev. 0.33 6/07 copyright ? 200 7 by silicon laborato ries si3226/7 si3208/9 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si3226/7 si3208/9 d ual p ro slic ? with dc-dc c ontroller features applications description the dual proslic ? is a family of low-voltage cmos devices that integrate both slic and codec functionality into a sing le ic. in combination with a linefeed ic (lfic), they provide a complete tw o-channel analog telephone interface in accordance with all relevant lssgr, it u, and etsi specifications. the dual proslic devices (si3226/7) operate from a single 3.3 v supply and interface to standard pcm/spi or gci bus digital interfaces. the lfics (si3208/9) perform all high-voltage functions and operate from a 3.3 v supply as well as high-voltage battery supplies. the si3208 is rated for ?110 v, and the si3209 is rated for ? 135 v. the dual proslic devices are available in a 64-pin thin quad flat package (tqfp), and the lfics are available in a 40-pin, quad flat no-lead package (qfn). functional block diagram performs all borscht functions ideal for short- or long-loop applications internal balanced or unbalanced ringing low power consumption software-programmable parameters: ringing frequency, amplitude, cadence, and waveshape two-wire ac impedance transhybrid balance dc current loop feed (10?45 ma) loop closure and ring trip thresholds ground key detect threshold integrated dc-dc controller wideband codec (si3227) low-power sleep mode on-hook transmission loop or ground start operation smooth polarity reversal dtmf generator/decoder a-law/-law companding, linear pcm pcm and spi bus digital interfaces with programmable interrupts gci/iom-2 mode support 3.3 v operation gr-909 loop diagnostics audio diagnostics with loopback pb-free/rohs-compliant packaging customer premises equipment (cpe) optical network terminals (ont) private branch exchange (pbx) cable emtas, atas, voip gateways linefeed ring tip ring tip linefeed spi control interface pcm/ gci interface dsp dtmf & tone gen programmable ac impedance and hybrid caller id ringing generator adc dac codec adc dac codec slic linefeed control linefeed monitor slic linefeed control linefeed monitor channel 1 channel 2 dc-dc controller line diagnostics pll pclk fsync drx dtx cs sdi sdo sclk int rst si3226 si3206 dc-dc bom vdc vbat linefeed ring tip ring tip linefeed spi control interface pcm/ gci interface dsp dtmf & tone gen programmable ac impedance and hybrid caller id ringing generator adc dac codec adc dac codec adc dac codec adc dac codec slic linefeed control linefeed monitor slic linefeed control linefeed monitor channel 1 channel 2 dc-dc controllers line diagnostics pll pclk fsync drx dtx cs sdi sdo sclk int rst si3226/7 dc-dc bom vdc vbat si3208/9 patents pending ordering information see page 33.
si3226/7 si3208/9 2 preliminary rev. 0.33
si3226/7 si3208/9 preliminary rev. 0.33 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application ci rcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.1. dc feed characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2. linefeed operat ing states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3. line voltage and current m onitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4. power monitoring and power fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5. thermal overload shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6. power dissipation considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.7. loop closure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.8. ground key detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.9. ringing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10. polarity reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.11. two-wire impedance synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.12. transhybrid balance filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.13. tone generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.14. dtmf detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.15. dc-dc controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.16. wideband audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.17. spi control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.18. pcm interface and compand ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.19. general circuit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.20. metallic loop testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. pin descriptions: si3226/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 6. pin descriptions: si3208/9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8. package outline: 64-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 9. package outline: 40-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
si3226/7 si3208/9 4 preliminary rev. 0.33 1. electrical specifications table 1. absolute maximum ratings and thermal information 1 parameter symbol test condition value unit operating temperature range t a ?40 to 85 c storage temperature range t stg ?55 to 150 c thermal resistance, typical 2 tqfp-64 ja 25 c/w continuous power dissipation 3 tqfp-64 p d t a =85c 1.6 w thermal resistance, typical 2 qfn-40 ja 32 c/w continuous power dissipation 4 qfn-40 p d t a =85c 1.7 w si3226/7 supply voltage v dd1 ? v dd4 ?0.5 to 4.0 v digital input voltage v ind ?0.3 to 3.6 v si3208 supply voltage v dd ?0.5 to 4.0 v battery supply voltage 5 v bat continuous +0.4 to ?110 v pulse < 10 s +0.4 to ?118 v tip, ring current i tip , i ring 100 ma si3209 supply voltage v dd ?0.5 to 4.0 v high battery supply voltage 5 v bat continuous +0.4 to ?135 v pulse < 10 s +0.4 to ?143 v tip, ring current i tip , i ring 100 ma notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. 2. the thermal resistance of an exposed pad package is a ssured when the recommended printed circuit board layout guidelines are followed correctly. the specified performa nce requires that the exposed pad be soldered to an exposed copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal/bottom copper plane. 3. operation of the si3226 or si3227 above 125 c j unction temperature may degrade device reliability. 4. si3208 and si3209 are equipped with on-chip thermal limiting ci rcuitry that shuts down the circuit when the junction temperature exceeds the thermal shutdown threshold. the thermal shutdown threshold should normally be set to 145 c; when in the ringing state the thermal shutdown may be set to 200 c. for optimal reliability long term operation of the si3208/si3209 above 150 c juncti on temperature should be avoided. 5. the dv/dt of the voltage applied to the vbat pins must be limited to 10 v/s.
si3226/7 si3208/9 preliminary rev. 0.33 5 table 2. recommended operating conditions parameter symbol test condition min * typ max * unit ambient temperature t a f-grade 0 25 70 o c ambient temperature t a g-grade ?40 25 85 o c supply voltage, si3226/7 v dd1 ?v dd4 3.13 3.3 3.47 v supply voltage, si3208/si3209 v dd 3.13 3.3 3.47 v battery voltage, si3208 v bat ?9 ? ?110 v battery voltage, si3209 v bat ?9 ? ?135 v *note: all minimum and maximum specificatio ns are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. table 3. 3.3 v power supply characteristics 1 (v dd =3.3v, t a = 0 to 70 oc for f-grade, ?40 to 85 oc for g-grade) parameter symbol test condition min typ max unit high impedance, reset i dd v t and v r = hi-z rst =0 ?2.4?ma i vbat ?0?ma high impedance, open current i dd v t and v r = hi-z ? 9.7 ? ma i vbat ?0.6?ma forward/reverse sleep, on-hook current i dd v tr = ?48 v ? 15 ? ma i vbat ?1.2?ma forward/reverse active, on-hook current i dd v tr = ?48 v ? 24 ? ma i vbat ?1.2?ma forward/reverse active, off-hook current i dd i loop =30ma r load =50 ?43?ma i vbat ? 3.1 + i loop ?ma forward/reverse oht, on-hook current i dd v tr = ?48 v ? 43 ? ma i vbat ?1.6?ma tip/ring open, on-hook current i dd v t or v r = ?48 v v r or v t = hi-z ?23?ma i vbat ?0.6?ma ringing current i dd v tr =55v rms + 0 v dc balanced, sinusoidal, f = 20 hz r load = 5 ren = 1400 ?26?ma i vbat ?2.3 + i ave ?ma notes: 1. all specifications are for a single channel of si3226/7 usin g si3208/9 linefeed ic and based on measurements with all channels in the same operating state. 2. i loop is the dc current in the subscr iber loop during the off-hook state. 3. i ave is the average of the full-wave rectified cu rrent in the subscriber loop during ringing (i ave = i peak x 2/ ).
si3226/7 si3208/9 6 preliminary rev. 0.33 table 4. ac characteristics (v dd = 3.13 to 3.47 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter test condition min typ max unit tx/rx performance overload level 2.5 ? ? v pk overload compression 2-wire ? pcm figure 6 ? ? single frequency distortion 1 2-wire ? pcm or pcm ? 2-wire: 200hz to 3.4khz ???65db pcm ? 2-wire ? pcm: 200 hz ? 3.4 khz, 16-bit linear mode ???65db signal-to-(noise + distortion) ratio 2 200hz to 3.4khz d/a or a/d 8-bit active off-hook, and oht, any z t figure 5 ? ? audio tone generator signal-to- distortion ratio 2 0 dbm0, active off-hook, and oht, any z t 46 ? ? db intermodulation distortion ? ? ?41 db gain accuracy 2 2-wire to pcm or pcm to 2-wire 1014 hz, any gain setting v dd1 ?v dd4 = 3.3 v 5% ?0.2 ? 0.2 db attenuation distortion vs. freq. 0 dbm 0 see an317 group delay vs. frequency gain tracking 3 1014 hz sine wave, reference level ?10 dbm signal level: ???? 3 db to ?37 db ? ? 0.25 db ?37 db to ?50 db ? ? 0.5 db ?50 db to ?60 db ? ? 1.0 db round-trip group delay 1014 hz, within same time-slot ? 450 500 s crosstalk between channels tx or rx to tx tx or rx to rx 0dbm0, 300hz to 3.4khz 300hz to 3.4khz ? ? ? ? ?75 ?75 db db 2-wire return loss 4 200hz to 3.4khz 26 30 ? db transhybrid balance 4 300hz to 3.4khz 26 30 ? db noise performance idle channel noise 5 c-message weighted ? 8 12 dbrnc psophometric weighted ? ?80 ?78 dbmp psrr from v dd1 ?v dd4 rx and tx, dc to 3.4 khz 40 ? ? db notes: 1. the input signal level should be 0 dbm0 for frequencies greater than 100 hz. for 100 hz and below, the level should be ?10 dbm0. the output signal magnitude at any other fr equency is smaller than the maximum value specified. 2. analog signal measured as v tip ? v ring . assumes ideal line impedance matching. 3. the quantization errors inherent in the /a-law compand ing process can generate slightly worse gain tracking performance in the signal range of 3 to ?37 db for signal frequencies that are integer divisors of the 8 khz pcm sampling rate. 4. v dd1 ?v dd4 = 3.3 v, v bat = ?52 v, no fuse resistors; r l = 600 , z s =600 synthesized using rs register coefficients. 5. the level of any unwanted tones wit hin the bandwidth of 0 to 4 khz does not exceed ?55 dbm.
si3226/7 si3208/9 preliminary rev. 0.33 7 longitudinal performance longitudinal to metallic/pcm balance (forward or reverse) 200 hz to 1 khz 58 60 ? db 1khz to 3.4khz 53 58 ? db metallic/pcm to longitudinal bal- ance 200 hz to 3.4 khz 40 ? ? db longitudinal impedance 200 hz to 3.4 khz at tip or ring ? 50 ? longitudinal current per pin active off-hook 200hz to 3.4khz ??30ma dc current differential ? ? 45 ma common mode ? ? 30 ma differential + common mode ? ? 45 ma table 4. ac characteristics (continued) (v dd = 3.13 to 3.47 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter test condition min typ max unit notes: 1. the input signal level should be 0 dbm0 for frequencies greater than 100 hz. for 100 hz and below, the level should be ?10 dbm0. the output signal magnitude at any other fr equency is smaller than the maximum value specified. 2. analog signal measured as v tip ? v ring . assumes ideal line impedance matching. 3. the quantization errors inherent in the /a-law compand ing process can generate slightly worse gain tracking performance in the signal range of 3 to ?37 db for signal frequencies that are integer divisors of the 8 khz pcm sampling rate. 4. v dd1 ?v dd4 = 3.3 v, v bat = ?52 v, no fuse resistors; r l = 600 , z s =600 synthesized using rs register coefficients. 5. the level of any unwanted tones wit hin the bandwidth of 0 to 4 khz does not exceed ?55 dbm.
si3226/7 si3208/9 8 preliminary rev. 0.33 table 5. linefeed characteristics (v dd = 3.13 to 3.47 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter symbol test condition min typ max unit maximum loop resistance r loop r dc,max =430 i loop =18ma, v bat = ?52v ? ? 2000 dc loop current accuracy i lim =18ma ? ? 10 % dc open circuit voltage accuracy active mode; v oc =48v, v tip ? v ring ?? 4 v dc differential output resistance r do i loop < i lim 160 ? 640 dc on-hook voltage accuracy?ground start v ohto i ring si3226/7 si3208/9 preliminary rev. 0.33 9 loop current sense accuracy accuracy of boundaries for each output code; i loop =18ma ?710% power alarm threshold accuracy power threshold = 300 mw ? ? 25 % table 6. monitor adc characteristics (v dd = 3.13 to 3.47 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter symbol test condition min typ max unit differential nonlinearity (8-bit resolution) dnle ? ? 1 lsb integral nonlinearity (8-bit resolution) inle ? ? 1 lsb gain error ? ? 5 % table 7. si3208/si3209 characteristics (v dd = 3.13 to 3.47 v, v bat = ?15 to ?130 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter symbol test condition min typ max unit tip/ring pull-down transistor saturation voltage v cm v ring ? v bat (forward) v tip ? v bat (reverse) v ac =2.5v pk i out =22ma i out =60ma ? ? 3 ? ? 3.5 v v tip/ring pull-up transistor saturation voltage v ov gnd ? v tip (forward) gnd ? v ring (reverse) v ac =2.5v pk i out =22ma i out =60ma ? ? 3 ? ? 3.5 v v open state tip/ring leakage current i lkg r l =0 ?? 150 a table 5. linefeed characteristics (continued) (v dd = 3.13 to 3.47 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter symbol test condition min typ max unit *note: ringing amplitude is set for 93 v peak and measured at tip-ring using no series protection resistance.
si3226/7 si3208/9 10 preliminary rev. 0.33 table 8. dc characteristics (v dd = 3.13 to 3.47 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter symbol test condition min typ max unit high level input voltage v ih 0.7 x v dd ?5.25v low level input voltage v il ? ? 0.3 x v dd v high level output voltage v oh i o =4ma v dd ?0.6 ? ? v low level output voltage v ol dtx, sdo, int , sdithru: i o =?4ma ??0.4v gpio1 a/b, gpio2 a/b: i o =?40ma ? ? 0.72 sdithru internal pullup resistance 35 50 ? k relay driver source impedance r out v dd1 ?v dd4 =3.13v io < 28 ma ?63? relay driver sink impedance r in v dd1 ?v dd4 =3.13v io < 85 ma ?11? input leakage current i l ??10a table 9. switching characteristics?general inputs 1 (v dd = 3.13 to 5.25 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade, c l =20pf) parameter symbol min typ max unit rise time, reset t r ?? 5 ns reset pulse width, gci mode 2,3 t rl 33/pclk ? ? s reset pulse width, spi daisy chain mode 3 t rl 33/pclk ? ? s notes: 1. all timing (except rise and fall time) is referenced to the 50% level of the waveform. input test levels are v ih =v dd ? 0.4 v, v il = 0.4 v. rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. the minimum reset pulse width assumes the sdithru pin is tied to ground via a pulldown resistor no greater than 10 k per device. 3. the minimum reset pulse width is 33/pclk frequency (i.e. 33/8.192 mhz = 4 s).
si3226/7 si3208/9 preliminary rev. 0.33 11 figure 1. spi timing diagram table 10. switching characteristics?spi (v dda = 3.13 to 5.25 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade, c l =20pf) parameter symbol test conditions min typ max unit cycle time sclk t c 62 ? ? ns rise time, sclk t r ? ? 25 ns fall time, sclk t f ? ? 25 ns delay time, sclk fall to sdo active t d1 ? ? 20 ns delay time, sclk fall to sdo transition t d2 ? ? 20 ns delay time, cs rise to sdo tri-state t d3 ? ? 20 ns setup time, cs to sclk fall t su1 25 ? ? ns hold time, cs to sclk rise t h1 20 ? ? ns setup time, sdi to sclk rise t su2 25 ? ? ns hold time, sdi to sclk rise t h2 20 ? ? ns delay time between chip selects t cs 220 ? ? ns sdi to sdithru propagation delay t d4 ? 4 10 ns note: all timing is referenced to the 50% level of the waveform. input test levels are v ih =v ddd ?0.4 v, v il =0.4v sclk cs sdi t h1 t d3 sdo t d1 t d2 t su1 t r t f t su2 t h2 t cs t c sdithru t d4
si3226/7 si3208/9 12 preliminary rev. 0.33 table 11. switching characteristics?pcm highway interface (v dd = 3.13 to 5.25 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade, c l =20pf) parameter symbol test conditions min 1 typ 1 max 1 units pclk period t p 122 ? 3906 ns valid pclk inputs ? ? ? ? ? ? ? ? 512 768 1.024 1.536 1.544 2.048 4.096 8.192 ? ? ? ? ? ? ? ? khz khz mhz mhz mhz mhz mhz mhz fsync period 2 t fs ?125 ?s pclk duty cycle tolerance t dty 40 50 60 % fsync jitter tolerance t jitter ? ? 120 ns rise time, pclk t r ? ? 25 ns fall time, pclk t f ? ? 25 ns delay time, pclk rise to dtx active t d1 ? ? 20 ns delay time, pclk rise to dtx transition t d2 ? ? 20 ns delay time, pclk rise to dtx tristate 3 t d3 ? ? 20 ns setup time, fsync to pclk fall t su1 25 ? ? ns hold time, fsync to pclk fall t h1 20 ? ? ns setup time, drx to pclk fall t su2 25 ? ? ns hold time, drx to pclk fall t h2 20 ? ? ns fsync pulse width t wfs t p ?125s?t p notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih ? v i/o ?0.4v, v il =0.4v. 2. fsync source is assumed to be 8 khz under all operating conditions. 3. spec applies to pclk fall to dtx tristate when that mode is selected.
si3226/7 si3208/9 preliminary rev. 0.33 13 figure 2. pcm highway interface timing diagram table 12. switching characteristics?gci highway serial interface (v dd = 3.13 to 5.25 v, t a = 0 to 70 c for f-grade, ?40 to 85 c for g-grade) parameter 1 symbol test conditions min typ max units pclk period (2.048 mhz pclk mode) t p ?488? ns pclk period (4.096 mhz pclk mode) t p ?244? ns fsync period 2 t fs ?125? s pclk duty cycle tolerance t dty 40 50 60 % fsync jitter tolerance t jitter ? ? 120 ns rise time, pclk t r ? ? 25 ns fall time, pclk t f ? ? 25 ns delay time, pclk rise to dtx active t d1 ? ? 20 ns delay time, pclk rise to dtx transition t d2 ? ? 20 ns delay time, pclk rise to dtx tristate 3 t d3 ? ? 20 ns setup time, fsync rise to pclk fall t su1 25 ? ? ns hold time, pclk fall to fsync fall t h1 20 ? ? ns setup time, drx transi tion to pclk fall t su2 25 ? ? ns hold time, pclk falling to drx transition t h2 20 ? ? ns fsync pulse width t wfs t p /2 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih =v o ? 0.4 v and v il =0.4v. rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. fsync source is assumed to be 8 khz under all operating conditions. 3. specification applies to pclk fall to dtx tristate when that mode is selected. pclk drx fsync dtx t d1 t d2 t su2 t h2 t d3 t r t p t su1 t h1 t f t fs t wfs
si3226/7 si3208/9 14 preliminary rev. 0.33 figure 3. gci highway interface timing diagram (2.048 mhz pclk mode) figure 4. gci highway interface timing diagram (4.096 mhz pclk mode) t su1 t h1 t p t r t f t h2 t d3 t d2 t d1 pclk fsync drx dtx t fs t su 2 frame 0, bit 0 frame 0, bit 0 t su1 t h1 t c t r t f t su2 t h2 t d3 t d2 t d1 pclk fsync drx dtx t fs frame 0, bit 0 frame 0, bit 0
si3226/7 si3208/9 preliminary rev. 0.33 15 figure 5. transmit and receive path sndr figure 6. overload compression performance acceptable 123456789 1 2 3 4 5 6 7 8 9 0 2.6 acceptable region fundamental input power (dbm0) fundamental output power (dbm0)
si3226/7 si3208/9 16 preliminary rev. 0.33 2. typical application circuits gpio1a dcdrva dcffa vdda svbatb dcffb dcdrvb sdchb sdclb gpio1a gpio1a gpio1a gpio1a gpio1a gpio1a gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a sdcha vddd vddc sdcla vddd gpio2b vdda svbata gpio2b gpio2b gpio2b gpio2b gpio2b gpio2b gpio2b gpio2b svbata vddc gpio1b gpio1b gpio1b gpio1b gpio1b gpio1b gpio1b gpio1b dcdrvb dcffa dcdrva dcffb sdcha sdcla sdchb gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a gpio2a sdclb svbatb gpio1b vcc_jumper vcc vbata vcc vin vbatb vbata vin vbatb vcc vbrng vbatb vin vbrng vbata drx pclk fsync /reset dtx /cs sdi sclk sdithru sdo /int pcm bus spi bus dc/dc converter b dc/dc converter a pcm mode select r15 dc/dc converter a dc/dc converter b r16 mode select gnd vcc x gci mode - 1x pclk (2.048 mhz) gci mode - 2x pclk (4.096 mhz) pcm mode gnd gnd vcc c7 0.1uf c7 0.1uf r17 137k 1% r17 137k 1% r15 10k r15 10k dcdc2 dcdc vout vin dcff dcdrv sdch sdcl gnd r16 10k r16 10k r13 10k r13 10k r2 49.9k 0.5% r2 49.9k 0.5% 1 1 2 2 3 3 4 4 5 5 6 6 j1 rj-11 j1 rj-11 r206 1.58m r206 1.58m c3 10uf c3 10uf c100 0.1uf 10% c100 0.1uf 10% r200 825k 1% r200 825k 1% prot2 protection tip ring tip_ext ring _ext vbat egnd vbrng r207 1.58m r207 1.58m r100 825k 1% r100 825k 1% c2 0.1uf c2 0.1uf prot1 protection tip ring tip_ext ring _ext vbat egnd vbrng r107 1.58m r107 1.58m c5 0.1uf c5 0.1uf c200 0.1uf 10% c200 0.1uf 10% 1 1 2 2 3 3 4 4 5 5 6 6 j2 rj-11 j2 rj-11 l1 10uh 180ma l1 10uh 180ma c1 10uf c1 10uf c4 0.1uf c4 0.1uf c6 10uf c6 10uf r106 1.58m r106 1.58m pwroa sringdca sringaca stipaca stipdca cappa capma svbata gpio1a/stipca gpio2a/sringca svdc csb fsync sdi hvclka sclk hvdata sdithru sdo dcffa sdcha sdcla dcdrva vddc dcdrvb sdclb sdchb dcffb gndd vddd vddreg dtx dtxenb hvclkb pclk drx intb resetb gpio2b/sringcb gpio1b/stipcb svbatb capmb cappb stipdcb stipacb sringacb sringdcb pwrob dringb uringb dtipb utipb ibiasb caplb iref qgnd gnda vdda isns ibiasa utipa dtipa uringa dringa si3226 si3226 r19 10k r19 10k c8 4.7nf 10% c8 4.7nf 10% dcdc1 dcdc vout vin dcff dcdrv sdch sdcl gnd lfi line interface isns hvdata gnd vcc vbata vbatb ibiasb sringdcb dtipa utipa dtipb utipb hvclka dringa uringa stipaca hvclkb dringb uringb stipacb sringaca sringacb stipdca stipdcb ibiasa sringdca tipa tipb ringa ringb figure 7. si3226/7 (2 lines)
si3226/7 si3208/9 preliminary rev. 0.33 17 vout dcdrv sdch sdcl gnd vin vin vin notes: 1) component values and ratings are shown in the bill of materials. 2) vin and vout are defined in the bill of materials. mosfet driver c120 c120 r125 r125 r126 r126 d121 d121 c121 c121 l120 l120 d122 d122 c122 c122 r122 r122 q120 q120 c127 c127 c125 c125 c128 c128 + c123 + c123 6 2 1 q121a q121a c126 c126 r123 r123 r121 r121 3 5 4 q121b q121b r124 r124 c124 c124 r127 figure 8. dc-dc converter (a)
si3226/7 si3208/9 18 preliminary rev. 0.33 vout dcdrv sdch sdcl gnd vin vin vin notes: 1) component values and ratings are shown in the bill of materials. 2) vin and vout are defined in the bill of materials. mosfet driver 6 2 1 q221a q221a l220 l220 r224 r224 3 5 4 q221b q221b c220 c220 c226 c226 c222 c222 c227 c227 r222 r222 r226 r226 d221 d221 c225 c225 d222 r225 r225 q220 q220 + c223 + c223 c221 c221 c224 c224 c228 c228 r223 r223 r221 r221 r227 r22 figure 9. dc-dc converter (b)
si3226/7 si3208/9 preliminary rev. 0.33 19 hw vcc tipa ringa tipb ringb gnd vbata vbatb stipaca sringaca stipdca sringdca utipa dtipa uringa dringa ibiasa isns hvdata hvclka stipacb sringacb stipdcb sringdcb utipb dtipb uringb dringb ibiasb hvclkb vbatb vbata vbata vbatb vcc vbata vbatb vcc si3208 vbat decoupling all resistors are 1% unless otherwise noted. global port connections c103 10nf 10% c103 10nf 10% c104 10nf 10% c104 10nf 10% c202 10nf 10% c202 10nf 10% r205 590k r205 590k r101 681k r101 681k iringn_1 ring_1 tip_1 iringp_1 itipn_1 itipp_1 ibias_1 isns vdd hvclk_1 hvdata itipp_2 itipn_2 iringp_2 iringn_2 ibias_2 hvclk_2 tip_2 ring_2 vbat_1 vbat_2 dgnd agnd hw_epad si3208 u100 si3208/qfn32 si3208 u100 si3208/qfn32 r201 681k r201 681k r203 301k r203 301k r104 301k r104 301k c203 10nf 10% c203 10nf 10% c102 10nf 10% c102 10nf 10% c101 10nf 10% c101 10nf 10% c201 10nf 10% c201 10nf 10% r102 681k r102 681k c204 10nf 10% c204 10nf 10% r202 681k r202 681k c107 0.1uf c107 0.1uf pcb3 pcb3 r103 301k r103 301k c205 0.1uf c205 0.1uf r204 301k r204 301k r105 590k r105 590k c105 0.1uf c105 0.1uf figure 10. linefeed (2 lines)
si3226/7 si3208/9 20 preliminary rev. 0.33 3. bill of materials table 13. bill of materials for si3226/7 (2 lines) quantity reference value rating tolerance dielectric pcb footprint manufacturer 2 c1, c6 10 f 6.3 v 20% y5v cc1210 venkel 2 c100, c200 0.1 f 6.3 v 10% x7r cc0603 venkel 4 c2, c4, c5, c7 0.1f 6.3 v 20% x7r cc0603 venkel 1 c3* 10f 6.3 v 20% y5v cc1210 venkel 1 c8 4.7 nf 6.3 v 10% x7r cc0603 venkel 1 l1* 10 h 180 ma 10% ind-nlc3225 tdk 1 r2 49.9 k 1/16 w 0.5% rc0603 venkel 4 r13, r15, r16, r19 10 k 1/10 w 5% rc0603 venkel 1r17137k 1/16 w 1% rc0603 venkel 2 r100, r200 825 k 1/10 w, 100 v 1% rc0805 venkel 4 r106*, r107*, r206*, r207* 1.58 m 1/10 w, 100 v 5% rc0805 venkel 1 u1 si3226 tqfp64 silabs *note: denotes optional component.
si3226/7 si3208/9 preliminary rev. 0.33 21 table 14. bill of materials for linefeed and dc-dc converters with |v out | < 90 v (2 lines) v in = +12 v nominal, |vout| < 90 v quantity reference value rating tolerance dielectric pcb footprint manufacturer 1 c120 10 f 25 v 20% x7r cc1210 venkel 1 c220* 10 f 25 v 20% x7r cc1210 venkel 2 c121, c221 0.1 f 25 v 10% x7r cc0603 venkel 2 c126, c226 0.1 f 25 v 20% x7r cc0603 venkel 2 c124, c224 0.1 f 100 v 20% x7r cc1210 venkel 2 c125*, c225* 0.1 f 100 v 20% x7r cc1210 venkel 2 c122, c222 0.22 f 100 v 20% x7r cc1812 venkel 2 c123, c223 3.3 f 100 v 20% al c2.5x6.3mm-rad panasonic 4 c127, c128, c227, c228 470 pf 25 v 10% x7r cc0402 venkel 2 d122, d222 bas21ht1 250 v,200 ma sod-323 on semi 2 d121, d221 stps2150a 150 v, 2.0 a do-214ac stmicro 2 l120, l220 15 h cdr74 sumida 2 q120, q220 fqt7n10 100 v, 2 w sot-223 fairchild 2 q121, q221 mmdt3946 sot-363 diodes inc. 2 r121, r221 0.1 1/4 w 1% rc1210 venkel 2 r122, r222 15 1/4 w 5% rc1206 venkel 2 r123, r223 220 1/16 w 5% rc0402 venkel 2 r124, r224 1 k 1/16 w 5% rc0402 venkel 2 r125, r225 150 k 1/16 w 5% rc0402 venkel 2 r126, r226 100 k 1/16 w 5% rc0402 venkel 2 r127, r227 2 1/8 w 5% rc0402 venkel 1 c107 0.1 f 25 v 10% x7r cc0603 venkel *note: denotes optional component.
si3226/7 si3208/9 22 preliminary rev. 0.33 4 c101, c102, c201, c202 10 nf 100 v 10% x7r cc0805 venkel 4 c103, c104, c203, c204 10 nf 100 v 10% x7r cc0805 venkel 2 c105, c205 0.1 f 100 v 20% x7r cc1210 venkel 4 r101, r102, r201, r202 681 k 1/10 w, 150 v 1% rc0805 venkel 4 r103, r104, r203, r204 301 k 1/16 w, 75 v 1% rc0603 venkel 2 r105, r205 590 k 1/10 w, 150 v 1% rc0805 venkel 1 u100 si3208 or si3209 qfn-40 silicon laboratories table 14. bill of materials for linefeed and dc-dc converters with |v out | < 90 v (2 lines) (continued) v in = +12 v nominal, |vout| < 90 v quantity reference value rating tolerance dielectric pcb footprint manufacturer *note: denotes optional component.
si3226/7 si3208/9 preliminary rev. 0.33 23 table 15. bill of materials for linefeed and dc-dc converters with |v out | < 135 v (2 lines) v in = +12 v nominal, |vout| < 135 v quantity reference value rating tolerance dielectric pcb footprint manufacturer 1 c120 10 f 25 v 20% x7r cc1210 venkel 1 c220* 10 f 25 v 20% x7r cc1210 venkel 2 c121,c221 0.1 f 25 v 10% x7r cc0603 venkel 2 c126,c226 0.1 f 25 v 20% x7r cc0603 venkel 2 c124,c224 0.1 f 200 v 20% x7r cc1210 venkel 2 c125*,c225* 0.1 f 200 v 20% x7r cc1210 venkel 2 c122,c222 0.22 f 200 v 20% x7r cc1812 venkel 2 c123,c223 3.3 f 160 v 20% al c2.5x6.3mm-rad panasonic 4 c127, c128, c227, c228 470 pf 25 v 10% x7r cc0402 venkel 2 d122, d222 bas21ht1 250 v,200 ma sod-323 on semi 2 d121, d221 stps2150a 150 v, 2.0 a do-214ac stmicro 2 l120, l220 15 h cdrh125 sumida 2 q120, q220 fqd7n20l 200 v , 2.5 w d-pak fairchild 2 q121, q221 mmdt3946 sot-363 diodes inc. 2 r121, r221 0.1 1/4 w 1% rc1210 venkel 2 r122, r222 15 1/4 w 5% rc1206 venkel 2 r123, r223 220 1/16 w 5% rc0402 venkel 2 r124, r224 1 k 1/16 w 5% rc0402 venkel 2 r125, r225 150 k 1/16 w 5% rc0402 venkel 2 r126, r226 100 k 1/16 w 5% rc0402 venkel 2 r127, r227 2 1/8 w 5% rc0402 venkel 1 c107 0.1 f 25 v 10% x7r cc0603 venkel *note: denotes optional component.
si3226/7 si3208/9 24 preliminary rev. 0.33 4 c101, c102, c201, c202 10 nf 200 v 10% x7r cc0805 venkel 4 c103, c104, c203, c204 10 nf 100 v 10% x7r cc0805 venkel 2 c105, c205 0.1 f 200 v 20% x7r cc1210 venkel 4 r101, r102, r201, r202 681 k 1/10 w, 150 v 1% rc0805 venkel 4 r103, r104, r203, r204 301 k 1/16 w, 75 v 1% rc0603 venkel 2 r105, r205 590 k 1/10 w, 150 v 1% rc0805 venkel 1 u100 si3209 qfn- 40 silicon laboratories table 15. bill of materials for linefeed and dc-dc converters with |v out | < 135 v (2 lines) (continued) v in = +12 v nominal, |vout| < 135 v quantity reference value rating toleran ce dielectric pcb footprint manufacturer *note: denotes optional component.
preliminary rev. 0.33 25 si3226/7 si3208/9 4. functional description the dual proslic ? chipset includes the si3226/7 low- voltage ic and the si3208/9 high-voltage linefeed ic. the dual proslic provides all slic, codec, dtmf detection, and signal generation functions needed for two complete analog telephone interfaces. the dual proslic performs all battery, over-voltage, ringing, supervision, codec, hybrid, and test (borscht) functions; it also supports extensive metallic loop testing capabilities. the si3226 provides a standard voice-band (200 hz? 3.4 khz) audio codec. the si3227 provides an audio codec with both wideband (50 hz?7 khz) and standard voice-band (200 hz? 3.4 khz) modes. the wideband mode provides an expanded audio band with a 16 khz sample rate for enhanced audio quality while the standard voice-band mode provides standard telephony audio compatibilit y. the si3226/7 provides two independent, programmable, dc-dc converter controllers, each of which reacts to line conditions to provide the optimal battery voltage required for each line-state. the linefeed chips (si3208/9) provide programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission. loop current and voltage are continuously monitored using an a/d converter in the si3226/7. the si3208 supports battery voltages up to 110 v, sufficient for most ringing signals. the si3209 supports battery voltages up to 130 v for higher-voltage ringing applications. the dual proslic supports balanced 5 ren ringing with or without a programmable dc offset. the available offset, frequency, waveshape, and cadence options are designed to ring the widest variety of terminal devices and to reduce external controller requirements. a complete audio transmit and receive path is integrated, including ac impedance and hybrid gain. these features are software-programmable, allowing a single hardware design to meet global requirements. digital voice data transfer occurs over a standard pcm bus. control data is transferred using a standard spi. the si3226/7 is available in a 64-pin tqfp; the si3208 is available in a 32-pin qfn, and the si3209 is available in a 40-pin qfn or a 48-pin etqfp. 4.1. dc feed characteristics dual proslic internal linefeed circuitry provides completely programmable dc feed characteristics. linefeed characteristics for each channel are independently configurable. when in the active state, each proslic channel operates in one of three dc linefeed operating regions: a constant-voltage region, a constant-current region, or a resistive region, as shown in figure 11. the constant- voltage region has a low resistance, typically 160 . the constant-current region approximates infinite resistance. figure 11. dual proslic dc feed characteristics 4.2. linefeed operating states the linefeed interface includes eight different register- programmable operating states as listed in table 16. the open state is the defa ult condition in the absence of any preloaded register settings. the device may also automatically enter the open state in the event of a linefeed fault condition. 4.3. line voltage and current monitoring the dual proslic continuously monitors the tip, ring, and battery voltages and currents via an on-chip adc and stores the resulting values in individual register addresses. additionally, the loop voltage (v tip ?v ring ), loop current, and longitudinal current values are calculated based on the tip and ring measurements and are stored in unique register locations for further processing. the adc updates all registers at a rate of 2 khz or greater. 4.4. power monitoring and power fault detection the dual proslic's line monitoring functions are used to continuously protect the linefeed ic (lfic) against excessive power conditions. the lfic contains an on- chip, analog sensing diode that provides real-time temperature data to the si3226/7 and turns off the lfic when a preset threshold is exceeded. the lfic status is reflected in a si3226/7 register bit. i loop (ma) i_rfeed v tr (v) i_ilim i_vlim resistive region constant i region constant v region v_vlim v_rfeed v_ilim
si3226/7 si3208/9 26 preliminary rev. 0.33 if the si3226/7 detects a fault condition or overpower condition on any channel, it automatically sets that channel to the open state and generates a "power alarm" interrupt. the interrupt can be masked, but the automatic transition to open cannot be masked. the various power alarms and linefeed faults supporting automatic intervention are described below. 1. lfic total power exceeded. 2. power exceeded in one or more transistors of a lfic internal transistor group (if capable of measuring individual power consumption). 3. excessive foreign current or voltage on tip and/or ring. 4. lfic thermal shutdown event; this event is automatically performed, and no intervention by the si3226/7 is required. 4.5. thermal overload shutdown if the lfic die temperature exceeds the maximum junction temperature threshold, tjmax, of 145 c or 200 oc or other programmed temperature threshold range, the lfic has the ability to shut itself down to a low-power state without any assistance from the si3226/7. the thermal shutdown circuit contains a sufficient amount of hysteresis and/or turn-on delay time so as to remain shut down during a power cross event, where 50 hz or 60 hz, 600 v, is connected to tip and/ or ring. 4.6. power dissipation considerations the dual proslic is designed to source loops up to 20 kft as well as short loop applications. the lfic provides all battery sourcing functions and is, therefore, the determining factor regarding power dissipation in a specific application. the dual proslic provides an on- chip dc-dc controller that can dynamically reduce the battery supply to ideally match the required line feed voltage. 4.7. loop closure detection the dual proslic provides a completely programmable loop closure detection mec hanism. the loop closure detection scheme provides two unique thresholds to allow hysteresis, and also includes a programmable debounce filter to eliminate false detection. a loop closure detect status bit pr ovides continuous status, and a maskable interrupt bit is also provided. table 16. linefeed operating states linefeed state description open output is high-impedance, and all line super vision functions are powered down. audio is powered down. this is the default state afte r powerup or following a hardware reset. this state can also be used in the presence of lin e fault conditions and to generate open switch intervals (osis). this state is used in line di agnostics mode as a high-z state during line- feed testing. a power fault condition may al so force the device into the open state. forward active reverse active linefeed circuitry and audio are active. in forw ard active state, the tip lead is more posi- tive than the ring le ad; in reverse active state, the ring lead is more positive than the tip lead. loop closure and ground key detect circuitry are active. forward oht reverse oht provides data transmission during an on-hook loop condition (e.g., transmitting caller id data between ringing bursts). linefeed circ uitry and audio are active. in forward oht state, the tip lead is more positive than t he ring lead; in revers e oht state, the ring lead is more positive than the tip lead. tip open provides an active linefeed on the ring lead and sets the tip lead to high impedance (>400 k ) for ground start operation in forward polarity. loop closure and ground key detect circuitry are active. ring open provides an active lin efeed on the tip lead and sets the ring lead to high impedance (>400 k ) for ground start operation in reverse polarity. loop closure and ground key detect circuitry are active. ringing drives programmable ringing signal onto ti p and ring leads with or without dc offset. line diagnostics the channel selected is put into diagno stic mode. in this mode, the selected channel has special diagnostic resources available.
preliminary rev. 0.33 27 si3226/7 si3208/9 4.8. ground key detection the dual proslic provides a ground key detect mechanism using a programmable architecture similar to the loop closure scheme. the ground key detect scheme provides two unique thresholds to allow hysteresis and also includes a programmable debounce filter to eliminate false detection. a ground key detect status bit provides contin uous status, and a maskable interrupt bit is also provided. 4.9. ringing generation the dual proslic provides the ability to generate a programmable sinusoidal or trapezoidal ringing waveform, with or without dc offset. the ringing frequency, wave shape, cadence, and offset are all register-programmable. using a balanced ringing scheme, the ringing signal is applied to both the tip and ring leads using dual ringing waveforms that are 180 out of phase with each other. the resulting ringing signal seen across tip-ring is twice the amplitude of the ringing waveform on either the tip or ring lead, which allows the ringing ci rcuitry to be forced to withstand only half the total ringing amplitude seen across tip-ring. 4.10. polarity reversal the dual proslic supports polarity reversal for message waiting and various other signaling modes. the ramp rate can be programmed for a smooth or abrupt transition to accommodate different application requirements. 4.11. two-wire impedance synthesis the ac two-wire impedance synthesis is generated on- chip using a dsp-based scheme to optimally match the output impedance of the dual proslic to the impedance of the subscriber loop and minimize the receive path signal reflected back onto the transmit path. most real or complex two-wire impedances can be generated by using the coefficient generator software to simulate the desired line conditions and generate the required register coefficients. 4.12. transhybrid balance filter the trans-hybrid balance function is implemented on- chip using a dsp-based scheme to effectively cancel the reflected receive path signal from the transmit path. the coefficient generator software is used to optimize the filter coefficients. 4.13. tone generators the dual proslic includes two digital tone generators that allow a wide variety of single- or dual-tone frequency and amplitude combinations. each tone generator has its own set of registers that hold the desired frequency, amplitude, and cadence to allow generation of dtmf and call progress tones for different requirements. the tones can be directed to either receive or transmit paths. 4.14. dtmf detection in dtmf, two tones generate a dtmf digit. one tone is chosen from the four possible row tones, and one tone is chosen from the four possible column tones. the sum of these tones constitutes one of 16 possible dtmf digits. the dual proslic performs dtmf detection using an algorithm to compute the dft for each of the eight dtmf frequencies and their second harmonics. at the end of the dft computation, the squared magnitudes of the dft results for the 8 dtmf fundamental tones are computed. the row and column results are sorted to determine the strongest tones, and checks are made to determine if the strongest row and column tones constitute a dtmf digit. 4.15. dc-dc controller the controller converts a single positive dc input voltage into an independent negative battery voltage for each channel. the controller operates a dc-dc converter circuit that converts a sing le positive dc input voltage into an independent negative battery voltage for each channel. in addition to eliminating external high-voltage power supplies, the dc-dc controller allows the dual proslic to dynamically control the battery voltage to the minimum required for any given operating state according to the programmed linefeed parameters. 4.16. wideband audio the si3226 supports a narrowband (200 hz?3.4 khz) audio codec. the si3227 supports a software- selectable wideband (50 hz?7 khz) and narrowband (200 hz?3.4 khz) audio codec. the si3227 wideband mode provides an expanded audio band at a 16-bit, 16 khz sample rate for enhanced audio quality while maintaining standard tele phony audio compatibility. wideband audio samples are transmitted and received on the pcm interface using two consecutive 8 khz frames.
si3226/7 si3208/9 28 preliminary rev. 0.33 4.17. spi control interface the controller interface to the dual proslic is a 4-wire interface modeled after microcontroller and serial peripheral devices. the interface consists of a clock (sclk), chip select (cs), serial data input (sdi), and serial data output (sdo). in addition, the dual proslic devices feature a serial da ta through output (sdithru) to support operation of up to eight devices (up to 16 channels) using a single ch ip select line. the device operates with both 8-bit and 16-bit spi controllers. 4.18. pcm interface and companding the dual proslic contains a flexible, programmable interface for the transmission and reception of digital pcm samples. pcm data tran sfer is controlled by the pcm clock (pclk) and frame sync (fsync) inputs as well as the pcm mode select, pcm transmit start, and pcm receive start settings. the interface can be configured to support from four to 128 8-bit time slots in each 125 s frame, corresponding to a pcm clock (pclk) frequency range of 256 khz to 8.192 mhz. 1.544 mhz is also supported. the dual proslic supports both -255 law (-law) and a-law companding formats in addition to 16-bit linear data mode with no companding. 4.19. general circuit interface the dual proslic supports an alternative communication interface to the spi and pcm control and data interface. the general circuit interface (gci) is used for transmission and reception of both control and data information onto a gci bus. the pcm and gci interfaces are both 4-wire interfaces and share the same pins. in gci mode, the four-wire spi control interface is used as hard- wired channel selector pins. the selection between pcm and gci modes is performed when coming out of reset using the sdithru pin. 4.20. metallic loop testing the dual proslic includes the ability to detect multiple fault conditions within the line card as well as on the t/r pair. 1. hazardous potential test?t his test checks for ac voltage >50 v rms or dc voltage >135 v on t-g or r- g. if a hazardous voltage is encountered, test access must release within two seconds of the time when it was initiated using a preset threshold. 2. foreign electromotive force test?checks t-g or r-g for ac voltage >10 v rms , dc voltage >6 v. uses same threshold as for hazardous voltage test. 3. resistive faults test?checks for dc resistance from t-r, t-g or r-g. any measurement <150 k is considered a resistive fault. 4. receiver-off-hook test?distinguishes between a t-r resistive fault and an off-hook condition. 5. ringers test?checks for the presence of ren across t-r. result are >0.175ren and <5ren for a valid load. 6. ac line impedance (line length)?t-r, t-g, and r-g. generate a tone at several specific frequencies (audio band) and measure the reflected signal amplitude (complex spectrum) that comes back (with transhybrid balance filter disabled). the reflected signal is then used to calculate the line impedance based on certain assumptions of wire gauge, etc. 7. line capacitance?t-r, t-g, r-g. generate a linear ramp function with polarity reversal, and measure the time constant. 8. ringer capacitance?this test uses the same procedure as the ringer test above but also measures the v/i phase relationship of the received signal (dc path) and then subtracts the delay to calculate the ringer capacitance. 9. ringing voltage verification?uses current voltage sensing capability. 10.test-in diagnostics?the dual proslic can switch in a preset load impedance to test the slic/codec functionality using a known set of conditions.
si3226/7 si3208/9 preliminary rev. 0.33 29 5. pin descriptions: si3226/7 table 17. si3226/7 pin descriptions pin number symbol i/o description 1 sringdca i ring dc sense input. 2 sringaca i ring ac sense input. 3 stipaca i tip ac sense input. 4 stipdca i tip dc sense input. 5 cappa i/o metallic loop filter ca pacitor-positive terminal. 6 capma i/o metallic loop filter ca pacitor-negative terminal. 7 svbata i battery sensing input. 8 svdc i dc-dc input power rail sensor. 9 gpio3a / pwroa i/o general purpose i/o / power offloading output. 10 gpio2a / sringca / trd2a i/o general purpose i/o / tip co urse sense input / test relay driver. 11 gpio1a / stipca / trd1a i/o general purpose i/o / tip course sense input / test relay driver. 12 cs i chip select input. 13 fsync i frame sync clock input. 14 sdi i serial port data input. 15 hvclka o line-driver ic clock output. 16 sclk i serial port bit clock input. 17 hvdata o line-driver ic data output 18 sdithru o serial data daisy chain output. 19 sdo o serial port data output. 20 dcffa i/o dc-dc bjt drive monitor. 21 sdcha i dc-dc current moni tor input-high terminal. 22 sdcla i dc-dc current moni tor input-low terminal. 23 dcdrva i/o dc-dc drive output. 24 vddc pwr dc-dc switch driver power supply. 25 dcdrvb o dc-dc drive output. 26 sdclb i dc-dc current moni tor input-low terminal. 27 sdchb i dc-dc current moni tor input-high terminal. 28 dcffb i/o dc-dc bjt drive monitor. 29 gndd gnd digital ground. 30 vddd pwr digital supply voltage. 31 pclk i pcm bus clock input. 32 hvclkb o line-driver ic clock output.
si3226/7 si3208/9 30 preliminary rev. 0.33 33 dtxen o transmit pcm enable output. 34 dtx o transmit pcm data output. 35 drx i receive pcm data input. 36 int o interrupt output. 37 rst i reset input. 38 vddreg i/o regulated core power supply. 39 gpio1b / stipcb / trd1b i/o general purpose i/o / tip course sense input / test relay driver. 40 gpio2b / sringcb / trd2b i/o general purpose i/o / tip co urse sense input / test relay driver. 41 gpio3b / pwrob i/o general purpose i/o / power offloading output. 42 svbatb i battery sensing input. 43 capmb i/o differential loop filt er capacitor-negative term. 44 cappb i/o differential loop filt er capacitor-positive term. 45 stipdcb i tip dc sense input. 46 stipacb i tip ac sense input. 47 sringacb i ring ac sense input. 48 sringdcb i ring dc sense input. 49 dringb o ring pull-down current driver output. 50 uringb o ring pull-up cu rrent driver output. 51 dtipb o tip pull-down cu rrent driver output. 52 utipb o tip pull-up current driver output. 53 ibiasb o line driver ic bias current output. 54 caplb o longitudinal balanc e calibration capacitor. 55 iref i current reference input. 56 qgnd i quiet ground reference input. 57 gnda gnd analog ground. 58 vdda pwr analog supply voltage. 59 isns i/o line current sense input. 60 ibiasa o line driver ic bias current output. 61 utipa o tip pull-up current driver output. 62 dtipa o tip pull-down cu rrent driver output. 63 uringa o ring pull-up cu rrent driver output. 64 dringa o ring pull-down current driver output. table 17. si3226/7 pin descriptions (continued) pin number symbol i/o description
si3226/7 si3208/9 preliminary rev. 0.33 31 6. pin descriptions: si3208/9 table 18. si3208/9 pin descriptions qfn pin # symbol i/o description 1 ic internal connection; leave to float. 2 nc no connect. 3 ring_1 i/o ring channel 1 input/output. 4 nc no connect. 5 tip_1 i/o tip channel 1 input/output. 6 nc no connect. 7 ic internal connection; leave to float. 8 iringn_1 i negative ring current control channel 1 input. 9 iringp_1 i positive ring curr ent control channel 1 input. 10 itipn_1 i negative tip current control channel 1 input. 11 itipp_1 i positive tip current control channel 1 input. 12 ibias_1 i current bias channel 1 input. 13 isns o current sense output. 14 vdd i ic supply voltage input. 15 hvclk_1 i high-voltage ic clock channel 1 input. 16 hvdata i/o high-voltage ic data input/output. 17 hvclk_2 i high-voltage ic clock channel 2 input. 18 dgnd i digital ground. 19 ibias_2 i current bias channel 2 input. 20 itipp_2 i positive tip current control channel 1 input. 21 itipn_2 i negative tip current control channel 2 input. 22 iringp_2 i positive ring curr ent control channel 2 input. 23 iringn_2 i negative ring current control channel 2 input. 24 ic internal connection; leave to float. 25 nc no connect. 26 tip_2 i/o tip channel 2 input/output. 27 nc no connect. 28 ring_2 i/o ring channel 2 input/output. 29 nc no connect. 30 ic internal connection; leave to float. 31 ic internal connection; leave to float. 32 vbat_2 i operating battery voltage channel 2 input. 33 nc no connect. 34 ic internal connection; leave to float.
si3226/7 si3208/9 32 preliminary rev. 0.33 35 nc no connect. 36 agnd i analog ground. 37 ic internal connection; leave to float. 38 ic internal connection; leave to float. 39 vbat_1 i operating battery voltage channel 1 input. 40 ic internal connection; leave to float. epad exposed die attach paddle. for adequate thermal management, the exposed die paddle should be soldered to a printed ci rcuit board pad that is connected to an electrically-isolated low-im pedance inner layer and/or back- side thermal plane(s) using multiple thermal vias. do not connect this pad to ground. table 18. si3208/9 pin descriptions (continued) qfn pin # symbol i/o description
si3226/7 si3208/9 preliminary rev. 0.33 33 7. ordering guide device description wideband audio package temp range si3226-x-fq dual proslic no tqfp-64 0 to 70 c si3226-x-gq dual proslic no tqfp-64 ?40 to 85 c si3227-x-fq dual proslic yes tqfp-64 0 to 70 c si3227-x-gq dual proslic yes tqfp-64 ?40 to 85 c si3208-x-fm 110 v dual lfic ? qfn-40 0 to 70 c si3208-x-gm 110 v dual lfic ? qfn-40 ?40 to 85 c si3209-x-fm 135 v dual lfic ? qfn-40 0 to 70 c si3209-x-gm 135 v dual lfic ? qfn-40 ?40 to 85 c notes: 1. all devices are lead-free and rohs compliant. 2. ?x? denotes product revision (a, b, c, etc.). 3. add an r at the end of the device to denote tape and reel options.
si3226/7 si3208/9 34 preliminary rev. 0.33 8. package outline: 64-pin tqfp figure 12 illustrates the package details for the si3226/7. t able 19 lists the values for th e dimensions shown in the illustration. figure 12. 64-pin thin quad flat package (tqfp)
si3226/7 si3208/9 preliminary rev. 0.33 35 table 19. 64-pin tqfp package dimensions dimension min nom max a??1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ? 0.20 d 12.00 bsc. d1 10.00 bsc. e 0.50 bsc. e 12.00 bsc. e1 10.00 bsc. l 0.45 0.60 0.75 aaa ? ? 0.20 bbb ? ? 0.20 ccc ? ? 0.08 ddd ? ? 0.08 q0 3.5 7 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant acd. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si3226/7 si3208/9 36 preliminary rev. 0.33 9. package outline: 40-pin qfn figure 13 illustrates the package details for the si3208/9. t able 20 lists the values for th e dimensions shown in the illustration. figure 13. 40-pin qfn package table 20. 40-pin qfn package dimensions dimension min nom max dimension min nom max a 0.80 0.90 1.00 e2 4.10 4.30 4.40 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 l1 0.03 0.05 0.08 d 6.00 bsc. aaa ? ? 0.10 d2 4.10 4.30 4.40 bbb ? ? 0.10 e 0.50 bsc. ccc ? ? 0.08 e 6.00 bsc. ddd ? ? 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vjjd-2. 4. recommended card reflow profile is per the jedec/ipc j-std-020c spec ification for small body components.
preliminary rev. 0.33 37 si3226/7 si3208/9 d ocument c hange l ist revision 0.2 to revision 0.32 added si3208 and si3209. removed si3203, si3205, and si3206. added pin-outs and package drawings for si3208 and si3209. updated pin-out for si3226. updated bill of materials. updated ?2. typical applicat ion circuits? and added dc-dc converter schematics. updated tables. revision 0.32 to revision 0.33 changed package type for si3208. deleted qfn-32 drawing. updated dc-dc converter schematic. updated bills of materials. updated max v bat values. updated thermal shutdown thresholds. updated si3208/9 pin descriptions.
si3226/7 si3208/9 38 preliminary rev. 0.33 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: proslicinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and prosli c are trademarks of silicon laboratories inc. other products or brand names mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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